Xilinx Field Programmable Gate Array, Part #: XC7Z007S-1CLG225I | FPGA | DEX integrated circuit The PEX 8617 architecture supports

The PEX 8617 architecture supports packet cut-thru with a maximum latency of 140ns (x4 to x4)

General Motors Engine Control Module Assembly Part #12692201

BRM:BL2345R

The output has been designed as a two wire current interface

NXP:S9S08DZ60F2MLF

Xilinx Field Programmable Gate Array, Part #: XC7Z007S-1CLG225I | FPGA | DEX integrated circuit The PEX 8617 architecture supportsXilinx Field Programmable Gate Array, Part #: XC7Z007S 1CLG225I integrates a feature rich dual core or single core ARM Cortex A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex A9 CPUs are the heart of the PS and also include on chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. Features ARM Cortex A9 Based Application Processor Unit (APU) Application